1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method and device including the formation of a borderless contact structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. For example, after implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas have been defined upon the substrate, alternating levels of interlevel dielectric and interconnect lines may be placed across the semiconductor topography to form a multi-level integrated circuit. Such a multi-level integrated circuit may include a plurality of layers and structures. For example, contact structures and/or vias may be formed within interlevel dielectric layers and in connection with interconnect lines. In some embodiments, the interlevel dielectric layers may include doped oxides. In particular, doped oxides may be used for forming self-aligned contact structures due to their etch selectivity to other materials. However, doped oxides typically need to be protected from the environment of the semiconductor fabrication process to prevent the formation of crystals within the doped oxide layer. As such, a semiconductor topography including a doped oxide interlevel dielectric typically includes a cap layer deposited thereon.
Forming various structures of an integrated circuit sometimes involves selectively removing portions of a material while other materials remain intact. In some cases, the formation of such structures involves patterning a photoresist upon the material. In such an embodiment, the photoresist may be patterned such that structures of particular dimensions may be fabricated. However, the use of a photoresist upon a layer or structure including a highly reflective material, such as metal, may cause problems. In particular, optical energy rays reflected off the upper surface of a metal layer may undesirably widen the pattern of the photoresist by exposing additional portions of the photoresist. In addition or alternatively, the reflected energy rays may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile. Such pattern issues may be particularly prevalent in sub-micron technologies.
Furthermore, the use of a photoresist above a nonplanar topography may cause problems due to the different reflective characteristics of the underlying steps and structures. More specifically, correctly patterning layers upon a topological surface containing elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d areas may be difficult using optical lithography since the all parts of the topography must be within the depth of focus of the lithography system. As such, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, the resolution of sub-micron (i.e., 1.0 micron or less) images may be particularly difficult, since the depth of focus required to pattern an upper surface of a semiconductor topography using a lithography tool of a particular wavelength may decrease with reductions in feature size.
To address these problems, an anti-reflective coating (ARC) may be formed beneath the photoresist to minimize the reflection of energy back toward the energy source during exposure of the photoresist. As such, a more accurate patterned photoresist profile may be formed. In addition, the ARC may planarize the topography such that the photoresist may be subsequently formed upon a planar surface. In this manner, lithography equipment may be used to a single depth of focus, thereby minimizing the distortions of the patterned image. Subsequent to the removal of the exposed portion of the underlying material, the ARC may be removed along with the photoresist such that additional layers and structures may be formed.
One example of a structure that may be formed within an integrated circuit is a borderless contact structure. A borderless contact structure may be referred to as a contact structure with a width greater than the width of the interconnect line over which it is formed. Such structures may also be referred to as xe2x80x9cunlanded contactsxe2x80x9d or xe2x80x9cnegative enclosure contactsxe2x80x9d. In order to form such a structure, a dielectric layer may be deposited upon an interconnect line and a trench with a width greater than the interconnect line may be etched within the dielectric layer to expose a portion of the interconnect line. The trench may be thereafter filled and planarized to form a borderless contact structure.
In some embodiments, the borderless contact structure may extend below the upper surface of the interconnect line. For example, the contact structure may extend along one or more sides of the interconnect line when the depth of the trench extends below the upper surface of the interconnect line. In some cases, the depth of the trench (and thus the borderless contact structure) may extend beyond the lower surface of the interconnect line into underlying portions of the semiconductor topography. Such an extension of a contact structure, generally referred to as punchthrough, may cause reliability issues and/or cause a device to be inoperable. As such, an etch stop layer may be formed above or below the interconnect line prior to formation of the trench such that the borderless contact structure does not extend into underlying portions of the semiconductor topography. Typically, such an etch stop layer includes silicon nitride since it adheres well to many materials and has good etch selectivity as compared to oxide. The use of such an etch stop layer, however, undesirably increases the process cycle time and fabrication costs of the device.
It would, therefore, be advantageous to develop a method for forming a borderless contact structure with fewer processing steps and layers.
The problems outlined above may be in large part addressed by a method for processing a semiconductor substrate. In particular, a method is provided which includes using an inorganic anti-reflective coating (IARC) layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in this embodiment, which includes an IARC layer arranged below an interconnect line. Such a topography may further include a contact structure with a width greater than the width of the interconnect line and arranged upon the interconnect line.
As stated above, the method described herein may include using an IARC layer as an etch stop to form a borderless contact structure. The use of such an IARC layer may include depositing an interlevel dielectric layer above the IARC layer and etching a trench within the interlevel dielectric layer. The etching process may be terminated upon exposure of the IARC layer. The borderless contact structure may then be formed in contact with the interconnect line by filling the trench with a conductive material. In a preferred embodiment, the method may include using the IARC layer as a pattern layer for an underlying interlevel dielectric layer prior to using the IARC layer as an etch stop. More specifically, the method may include depositing the IARC layer upon the interlevel dielectric layer and depositing a photoresist layer upon the IARC layer. The method may further include patterning the photoreisist layer and IARC layer to expose portions of the interlevel dielectric layer. Alternatively, the photoresist layer may be patterned to exposed portions of the IARC layer. The exposed portions of the interlevel dielectric layer and/or IARC layer may then be etched to form a trench.
The materials used for the IARC layer may have properties that aid in producing a photoresist profile that meets the design specifications of the device. More specifically, the materials used for the IARC layer may have properties that aid in minimizing the reflection of energy back toward the energy source and minimizing standing waves within the photoresist layer. In general, the properties that influence how an ensuing energy ray may be transmitted through a material may include the material""s refractive index and extinction coefficient. For example, the refractive index of a material may refer to the speed and angle at which an energy ray may transmit through the material. In this manner, it may be beneficial for the IARC layer to have approximately the same refractive index as an overlying resist layer in order to project the energy ray at a similar angle of incidence. The extinction coefficient of the material, on the other hand, may refer to the degree or amount by which the energy ray is lessened or xe2x80x9cabsorbedxe2x80x9d as it traverses through the material. In other words, the extinction coefficient of a material may correspond to the amount by which the intensity of an energy ray may be reduced by traveling a given distance. The extinction coefficient may also be referred to as the absorption constant/coefficient, attenuation index, or damping constant. As such, the extinction coefficient of a material may affect the amount of light that may be scattered from the surface of the underlying topography back to the resist.
In general, the refractive index and extinction coefficient may be dependent on the wavelength of the energy used, and thus may be dependent upon each other. As such, a material including a refractive index and an extinction coefficient that together minimize the reflection of energy back toward the energy source and minimize standing waves produced within the photoresist is preferably used as the IARC layer. For example, the IARC layer may include a refractive index and an extinction coefficient between, but not including those of silicon dioxide and silicon nitride. In particular, the refractive index may be between approximately 1.6 and approximately 2.0 and the extinction coefficient may be between approximately 0.3 and approximately 0.9. Materials may include different values of refractive indexes and extinction coefficients, however, depending on the characteristics of the material and process parameters of the patterning process. Regardless of the process parameters of the etch process, examples of materials with the aforementioned properties may include silicon oxynitride or silicon rich oxide.
The method as described herein may include, in addition to using the IARC layer as an etch stop layer, using the IARC layer for other purposes within a semiconductor fabrication process. For example, the method may include using the IARC layer as a polish stop layer prior to using the inorganic anti-reflective coating layer as an etch stop. In such an embodiment, the method may include filling a trench with a conductive material. The conductive material may be planarized such that an upper surface of the conductive material is substantially planar with an upper surface of the IARC layer. In this manner, the polishing process may be terminated upon coming in contact with the IARC layer. In some embodiments, the method may include using the inorganic anti-reflective coating layer as a cap layer over an underlying interlevel dielectric layer. In such an embodiment, the interlevel dielectric layer may include doped oxide. In addition or alternatively, the method may include using the inorganic anti-reflective coating layer as a punchthrough stop to prevent the borderless contact structure from contacting the underlying dielectric layer.
In some embodiments, the method may include patterning an interconnect line above an inorganic layer including anti-reflective properties. In addition, the method may include depositing an upper interlevel dielectric layer above the interconnect line and etching a trench within the upper interlevel dielectric layer. A borderless contact structure may then be formed in contact with the interconnect line. In some embodiments, the method may include depositing a lower interlevel dielectric layer upon the semiconductor topography, below the inorganic layer and prior to patterning the interconnect line. A lower trench may be etched within the lower interlevel dielectric layer and a contact structure formed therein prior to patterning the interconnect line. In some embodiments, forming the lower contact structure may include lining the lower trench with a barrier layer. In a preferred embodiment, the method may include depositing the inorganic layer upon the lower interlevel dielectric layer and depositing a resist layer upon the inorganic layer prior to etching the lower trench. The inorganic layer and resist layer may then be patterned to expose portions of the topography to be etched. Alternatively, the resist layer may be patterned to expose portions of the inorganic layer. In either embodiment, the exposed portions of the interlevel dielectric layer and/or inorganic layer may be etched to form the trench. The resist layer may be removed either prior to forming the contact structure or prior to patterning the interconnect line.
Consequently, the method as described herein may form a semiconductor topography which includes an IARC layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. Preferably, the IARC layer is in contact with the interconnect line. Moreover, the width of the contact structure is preferably greater than the width of the interconnect line. In some embodiments, the contact structure may contact an upper surface and one or more sides of the interconnect line. Alternatively, the contact structure may only contact the upper surface of the interconnect line. In either embodiment, the semiconductor topography may also include a lower interlevel dielectric layer arranged below the IARC layer as well as a second contact structure arranged within the lower interlevel dielectric layer. In some embodiments, the lower interlevel dielectric layer may include doped oxide. For example, the lower interlevel dielectric may include phosphorus silicate glass. Alternatively, the lower interlevel dielectric layer may include undoped oxide. Preferably, the IARC layer includes a refractive index and an extinction coefficient between, but not including those of silicon dioxide and silicon nitride. In particular, the refractive index may be between approximately 1.6 and approximately 2.0 and the extinction coefficient may be between approximately 0.3 and approximately 0.9. Materials may include different values of refractive indexes and extinction coefficients, however, depending on the characteristics of the material and process parameters of the patterning process. In either embodiment, the IARC layer may include silicon oxynitride or silicon rich oxide.
There may be several advantages to forming a borderless contact structure using the method as described herein. For example, such a method allows a borderless contact structure to be formed within a semiconductor topography without inducing punchthrough. In addition, the method does not require the deposition of a separate etch stop layer for the formation of the borderless contact structure. Moreover, an additional cap layer is not needed when a material underlying the borderless contact structure includes a doped oxide. The reduction in the number of such layers reduces the process time of the fabrication process, thereby saving time and money.